Pipelined Ripple Carry Adder

Overview

A pipelined ripple carry adder, built as part of a digital system design course. In a ripple carry adder, each bit position waits on the carry-out of the previous stage before it can produce a correct sum, so the carry effectively "ripples" across the full width of the adder one stage at a time. Pipelining breaks the chain into stages that can overlap across successive additions, trading a small amount of latency for higher throughput.

How it works

Each stage combines two input bits and the carry-in from the previous stage into a sum bit and a carry-out, and the carry-out only becomes valid once the previous stage has resolved. The animation above shows that dependency directly: the carry signal has to visibly travel from the least significant bit to the most significant bit before the final sum is correct, which is the defining trade-off of a ripple carry design compared to a carry look-ahead adder.

← Back to all projects